(1) Field of the Invention
The present invention relates to a process sequence used to simultaneously fabricate a first device type, comprised with features directed at improved reliability, and a second type of device, comprised with features directed at enhanced performance.
(2) Description of the Prior Art
The use of high voltage, input/output, (I/O), devices, along with core devices, which operate at a lower voltage than the I/O device counterparts, both located on a single semiconductor chip, has led to design compromises, regarding reliability and performance. To realize maximum performance, the core devices are fabricated featuring short channel regions. The use of the performance enhancing short channel regions, for the core devices, require such features as heavier channel doping, anti-punchthrough implant regions, and shallow, abrupt, source/drain regions. However the I/O devices, operating at higher voltages than the core device counterparts, benefit, in terms of reducing hot carrier effects, (HCE), via the use of a non-sharp, source/drain region, featuring a graded dopant profile. To obtain the graded dopant profile, needed to reduce hot carrier reliability phenomena, prominent with the higher operating voltages used by the I/O devices, transient enhanced diffusion, (TED), of the ion implanted species, used for the lightly doped source/drain, (LDD), region, is needed. However another important factor to be considered is the lack of diffusion, or the fixed position, of ion implanted species, after being subjected an anneal cycle, such as the activation anneal cycle, used for the LDD implanted ions. Therefore the graded LDD dopant profile, of the I/O device, has to be formed prior to anneal cycles used to activate implanted species, used for the core device. Therefore to simultaneously fabricate I/O, and core devices, on a single semiconductor chip, and to create the LDD regions, needed for reliability of the I/O device, and for performance of the core device, a novel process sequence is needed.
This invention will describe a process sequence, in which the desired sharp dopant profile, needed for the LDD of the core device, and the graded, less abrupt dopant regions, needed for the LDD, I/O devices, are realized. This is accomplished by initially ion implanting the I/O, LDD region, followed by a furnace anneal, resulting in the desired graded, LDD profile, then followed by the ion implantation of the core device LDD region, and a subsequent activation anneal. Prior art, such as an article titled, "A Comprehensive Study of Performance and Reliability of P, As and Hybrid As/P n LDD Junctions for Deep-Submicron CMOS Logic Technology", by Nayak et al, in IEEE ELECTRON DEVICE LETTERS, Vol. 18, No. 6, June 1997, describes a method in which the LDD is fabricated using both arsenic and phosphorous, to enhance performance, and preserve reliability. That prior art however, does not show the process described in this invention, in which both I/O and core devices, are simultaneously created, each exhibiting the desired dopant profile, achieved via the initial creation of the graded dopant regions of the I/O devices, followed by the fabrication of the core device, featuring a sharp, or abrupt, LDD region.